Various communication schemes have been proposed for data exchange among multiple devices. In particular, the Inter-Integrated Circuit (I2C) communication that transmits data via a serial interface is sometimes applied to communication between devices disposed near to each other, such as on the same board.
In the I2C communication, a normal I2C bus that connects the devices to each other is formed of two signal lines, a serial data (SDA) signal line and a serial clock (SCL) signal line.
The devices connected to an I2C bus are classified into either a master device or a slave device and normally, each has unique I2C address set therefor.
As illustrated in accompanying drawings of FIGS. 17A and 17B, a single master device (I2C Maser) 100 is connected to multiple (three in the drawings) slave devices (I2C Slaves) 200 via one set of I2C buses 300.
FIGS. 17A and 17B illustrate a typical I2C tree structure and a typical I2C communication procedure. The following description specifies the respective slave devices with the reference numbers 200-1, 200-2, and 200-3, but refers to a non-specified slave device with the reference number 200.
In the example of FIGS. 17A and 17B, I2C slave addresses (I2C addresses) 0xA0, 0xA1, and 0xA2 are set for the slave devices 200-1, 200-2, and 200-3, respectively.
The master device 100 designates a slave device 200 that is to be the communication counterpart using the corresponding I2C slave address and then serially forwards data to and from the designated slave device 200. The I2C communication uses open-drain signal lines to connect devices, so that a set of I2C buses 300 is capable of connecting a single master device 100 to two or more slave devices 200.
According to the specification of the I2C communication, the master device 100 makes one-to-one access to a slave device 200. Upon receipt of a command from the master device 100, the slave device 200 recognizes that the master device 100 is making access to the slave device 200 itself and then occupies the I2C bus 300 until the slave device 200 replies to the master device 100 with a response signal (acknowledgement (ACK)).
For example, when the master device 100 is to write data into a register of the slave device 200-3, the master device 100 outputs data to the I2C bus 300 as illustrated in FIG. 17A. Specifically, the master device 100 serially outputs the address (0xA2) of the slave device 200-3, a writing command (Write), a register address (Reg. add), and data to be written (not illustrated) to the I2C bus 300 (SDA signal line). Upon receipt of these pieces of data, the slave device 200-3 recognizes that the address 0xA2 represents an access to the device 200-3 itself and occupies the I2C bus 300 until the slave device 200-3 completes the data writing of the designated register and replies to the master device 100 with an ACK. FIG. 17B illustrates an example of the master device 100 writing data into a register of the slave device 200-1. The master device 100 writes data into another slave device 200 except for the slave device 200-3 in the same manner as the above.
When the master device 100 accesses multiple slave devices 200 to write the same data in the slave devices 200, the process of FIG. 17A or 17B is serially repeated as illustrated in, for example, FIG. 18. FIG. 18 illustrates procedure (steps S101-S120) performed when a single master device (MD) makes a writing access (Write) into five slave devices (SD#1-SD#5).
As illustrated in FIG. 18, the MD first designates the address of the SD#1 and transmits a writing command including a writing access starting signal “H (High; 1)” to the SD#1 (step S101). The SD#1 recognizes the writing command directed to the SD#1 by referring to the address from the MD and then receives the writing command (step S102). After the completion of data writing in obedience to the writing command, the SD#1 transmits an ACK signal “L (Low; 0)” to the MD (step S103). After receiving the ACK signal from the SD#1 (step S104), the MD makes access to the SD#2 in the same manner (steps S105-S108) as the process performed on the SD#1. After that, the MD sequentially makes access to the SD#3 (steps S109-S112); access to the SD#4 (steps S113-S116); and access to the SD#5 (steps S116-S120).
As described above, when the MD is to write the same data into multiple SDs set respective unique addresses therefor, the MD serially repeats the same process multiple times as many as the number of SDs as illustrated in FIG. 18. For example, when the same initial value is to be set into each SD in the I2C communication at a start of a server device including a single MD and N (integer of two or more) SDs, the MD repeats the same process N times. The time that the MD takes to complete the writing data into the last SD from the start of data writing into the first SD increases in proportional to the number N of SDs. This process is very inefficient because increase in the number N of SDs prolongs the time that the starting of the server device (data forwarding process) takes.
In view of the above inefficiency, the I2C communication sets the same I2C address (e.g., 0xA2) for multiple SDs 200 as illustrated in FIG. 19, so that the master device 100 transmits data simultaneously to the multiple slave devices 200, that is, I2C multicasting. This allows the master device 100 to simultaneously make writing access to the multiple slave devices 200. However, ACKs from the respective SDs 200 collide with each other on the I2C bus 300, which may break data exchanged between the master device 100 and a slave device 200. Simply setting the same I2C address to the multiple slave devices 200 for simultaneous transmission hardly succeeds in correct simultaneous access to the multiple SDs 200.